1. Field of the Invention
This invention relates to a complementary field effect element. More particularly, the invention relates to a complementary field effect element having a twin well construction and a method of producing the same.
2. Description of the Background Art
Heretofore, in CMOS circuits, latch-up, or a phenomenon in which a parasitic bipolar transistor is rendered conductive to cause a large current to flow between the power terminals of the CMOS circuit, has become a problem. If such latch-up takes place, an inconvenience occurs in which the circuit operation is obstructed or the IC itself is destroyed. Therefore, various methods for preventing the latch-up have heretofore been proposed. For example, such method is disclosed in Japanese Patent Laying-Open No.1-189955(1989).
FIGS. 9A through 9M are sectional views for explaining a process for producing CMOS circuits having a conventional latch-up preventive measure applied thereto. First, referring to FIG. 9M, CMOS circuits having a conventional latch-up preventive measure applied thereto will now be described. A conventional CMOS circuit comprises a P-type silicon substrate 1, a P-well 2 and N-well 3 formed adjacent each other on the P-type silicon substrate 1, n.sup.+ diffusion layers 4 and 5 serving as source and drain regions of an N channel transistor, a p.sup.+ diffusion layer 6 formed on the P-well 2 for fixing the well potential of the P-well 2, p.sup.+ diffusion layers 7 and 8 formed on the N-well 3 and serving as source and drain regions of a P channel transistor, an n.sup.+ diffusion layer 9 formed on the N-well 3 for fixing the well potential of the N-well 3, a gate electrode 11 formed on the P-well 2 between the n.sup.+ diffusion layers 4 and 5 with a gate oxide film sandwiched therebetween, a gate electrode 13 formed on the N-well between the p.sup.+ diffusion layers 7 and 8 with a gate oxide film 12 sandwiched therebetween, a field oxide film 14 for element isolation formed between the n.sup.+ diffusion layer 4 and p.sup.+ diffusion layer 7, and a p.sup.+ buried layer 15 formed in a region in the P-type silicon substrate 1 deeper than the P-well 2 and N-well 3 and extending parallel to the main surface of the P-type silicon substrate 1.
Referring to FIGS. 9A through 9M, the process for producing CMOS circuits having a conventional latch-up preventive measure applied thereto will now be described. As shown in FIG. 9A, an oxide film 21 of SiO.sub.2 is formed on the P-type silicon substrate 1. A nitride film 22 of Si.sub.3 N.sub.4 is formed on the oxide film 21. Boron B.sup.+ is implanted from top of the nitride film 22 with high energy by ion implantation method. Thereby, the p.sup.+ buried layer 15 for prevention of latch-up is formed. As shown in FIG. 9B, a resist 23 is patterned on the nitride film 22. The nitride film 22 is then etched with the resist 23 serving as a mask. As shown in FIG. 9C, the resist 23 is removed. Thermal oxidation is effected with the nitride film 22 used as a mask. Thereby, LOCOS (Local Oxidation of Silicon) isolation based on the formation of the field oxide film 14 is effected while activating the p.sup.+ buried layer 15. That is, since the crystal structure of the p.sup.+ buried layer 15 is amorphous immediately after ion implantation, the p.sup.+ buried layer 15 is crystallized utilizing heat employed in forming the field oxide film 14. This crystallization allows impurities to be introduced into a crystal lattice, thereby leading the p.sup.+ buried layer 15 to serve as a high impurity concentration buried layer. Subsequently, the nitride film 22 is removed. As shown in FIG. 9D, with a resist 25 used as a mask, phosphorus P.sup.+ is implanted with high energy by ion implantation method. Thereby, the N-well 3 is formed. Simultaneously, phosphorus P.sup.+ is implanted with low energy, thereby forming an implanted region 26 for V.sub.TH control. As shown in FIG. 9E, a resist 27 is patterned on a region other than the region which is to be formed with the P-well 2. With the resist 27 used as a mask, boron B.sup.+ is implanted with high energy. Thereby, the P-well 2 is formed. Boron B.sup.+ is implanted with low energy simultaneously with the formation of the P-well 2, whereby an implanted region 28 for V.sub.TH control is formed. As shown in FIG. 9F, the resist 27 is removed. Thereby, it follows that the well regions of the CMOS circuit have been formed. As shown in FIG. 9G, the oxide film 21 is removed. As shown in FIG. 9H, a gate oxide film 30 is formed in the region from which the oxide film 21 has been removed. The oxide film 21 is as thick as several 100 .mu.m and hence is not allowed to be used as a gate oxide film requiring a small thickness (100-200 .mu.m). Thus, the gate oxide film 30 need be formed. As shown in FIG. 9I, a polysilicon film 31 serving as a gate electrode is formed on the gate oxide film 30. As shown in FIG. 9J, the portions of the gate oxide film 30 and polysilicon film 31, formed in the regions other than the regions which are to be finally formed with the gate oxide films 10 and 12 and gate electrodes 11 and 13, are etched using photolithography. As shown in FIG. 9K, a resist 32 is formed in a region other than the regions which are to be formed with the n.sup.+ diffusion layers 4 and 5 serving as a source and a drain in the P-well 2 and the n.sup.+ diffusion layer 9 for fixing the well potential of the N-well 3. With the resist 32 used as a mask, As.sup.+ is implanted. Thereby, the diffusion layers 4 and 5 in the P-well 2 and the diffusion layer 9 in the N-well 3 are formed. As shown in FIG. 9L, the resist 32 is removed. A resist 33 is formed in a region other than the regions which are to be formed with the p.sup.+ diffusion layers 7 and 8 serving as a source and a drain in the N-well 3 and the p.sup.+ diffusion layer 6 for fixing the well potential of the P-well 2. With the resist 33 used as a mask, ion implantation of boron B.sup.+ is effected. Thereby, the p.sup.+ diffusion layers 7 and 8 in the N-well 3 and the p.sup.+ diffusion layer 6 in the P-well are formed. Finally, as shown in FIG. 9M, the resist 33 is removed and source/drain drive is effected to activate the impurities. Simultaneously therewith, the N-well 3 and P-well 2 are also activated. In this manner, the CMOS circuit having a conventional latch-up preventive measure applied thereto is formed.
FIG. 10 is a schematic view for explaining the arrangement of parasitic bipolar transistors and bulk-resistance components in the CMOS circuit shown in FIG. 9. The conventional latch-up preventive measure will now be described with reference to FIG. 10. First, the mechanism of latch-up will be described. The cause of latch-up occurs in both the P-well 2 and N-well 3. That is, the latch-up occurs due such as to the occurrence of hot carriers in the P-well 2 and hot carriers owing to a high electric field near the drain in the N-well 3. A description will now be given on the latch-up due to the hot carriers occurring in the P-well 2. For example, it sometimes happens that holes are produced as hot carriers in the P-well 2. When these holes flow to the diffusion layers 4 and 5 in the P-well 2, this means that currents flow through the bases of NPN transistors 103 and 104, so that collector currents equal to the base currents times current amplification factors flow. That is, currents flow from the N-well 3 to the p.sup.+ diffusion layers 4 and 5 in the P-well 2. At this time, currents hardly flow from the p.sup.+ diffusion layers 7 and 8 in the N-well 3 owing to the diffusion potential associated with the N-well 3. When a current flows from the n.sup.+ diffusion layer 9 in the N-well to the P-well 2, it flows through a bulk-resistance 201 of N-well 3. The voltage produced across said bulk-resistance 201 by said current raises the potential of the bases of the PNP transistors 101 and 102 to turn on PNP transistors 101 and 102. With the PNP transistors 101 and 102 turned on, a current flows through the P-type silicon substrate 1 which forms the collectors of the PNP transistors 101 and 102, and finally the current flows to the p.sup.+ diffusion layer 6 in the P-well 2. With this current flowing through a bulk-resistance 202a, a voltage is produced across said bulk-resistance 202a. This voltage raises the base potentials of the NPN transistors 103 and 104, thereby increasing the collector currents in the NPN transistors 103 and 104. As a result, the current flowing through the bulk-resistance 201 further increases. With a positive feedback applied in this manner, a large current remains flowing between V.sub.DD and V.sub.SS independently of the current due to holes, or hot carriers, which function as a trigger in the beginning. This is the mechanism by which latch-up occurs. Further, even if there is no carrier produced in the beginning, latch-up can occur in the case where noise from the outside makes the voltage on the n.sup.+ diffusion layer 5 in the P-well 2 lower than the V.sub.SS or makes the voltage on the p.sup.+ diffusion layer 8 in the N-well 3 higher than the V.sub.DD.
To prevent such latch-up, it has been common practice to form the p.sup.+ diffusion layer 15 shown in FIG. 9M. Thereby, the bulk-resistance value of the bulk-resistance 202b can be lowered. Consequently, the currents flowing through the collectors of the PNP transistors 101 and 102 flow downward to pass through the p.sup.+ buried layer 15. Therefore, even if the same currents as in the prior art flow from the p.sup.+ diffusion layers 7 and 8 in the N-well 3 to the p.sup.+ diffusion layer in the P-well 2 via the P-type silicon substrate 1, the voltage produced across the bulk-resistance 202b becomes lower. As a result, there is obtained an effect that the NPN transistors 103 and 104 are less easy to turn on. Further, since the p.sup.+ diffusion layer 15 is formed in the region corresponding to the bases of the NPN transistors 103 and 104, there is another effect that the gains of the NPN transistors 103 and 104 are decreased. In this manner, in the prior art, the p.sup.+ buried layer 15 is formed to extend parallel with the main surface of the P-type silicon substrate and in a region deeper than the P-well 2 and N-well 3 of the P-type silicon substrate, thereby lowering the bulk-resistance value of the bulk-resistance 202 which has been a cause for raising the base potentials of the NPN transistors 103 and 104 so as to prevent latch-up.
As described above, in the conventional CMOS circuit, the p.sup.+ buried layer 15 is formed in a region deeper than the region where the P-well 2 and N-well 3 of the P-type semiconductor substrate 1 are formed, so as to prevent latch-up.
However, as CMOS circuits are made finer such that the distance between the p.sup.+ diffusion layer 7 in the N-well 3 and the n.sup.+ diffusion layer 4 in the P-well is shorter, the carriers flowing through the PNP transistors 101 and 102 find it easier to pass through the wall between the N-well 3 and P-well 2 than through the p.sup.+ diffusion layer 15. This results in a disadvantage that the effect provided by the p.sup.+ buried layer 15 is greatly decreased.
That is, the collector currents of the PNP transistors 101 and 102 pass through the wall between the N-well 3 and the P-well 2 rather than through the buried layer 15, flowing into the P-well 2. And finally, it flows into the p.sup.+ diffusion layer 6 in the P-well 2. FIG. 11 is a schematic view for explaining parasitic transistors and bulk-resistance components when CMOS circuits are made finer. Referring to FIG. 11, with this current path, a new bulk-resistance 202c in the P-well 2 raises the base potentials of the NPN transistors 03 and 104, so that they are turned on, a fact which means that even if the bulk-resistance value of the bulk-resistance 202 is decreased by the p.sup.+ buried layer 15, there is no effect of making it less easy to turn on the NPN transistors 103 and 104. Further, since the currents flowing through the bases of the NPN transistors 103 and 104 do not pass through the p.sup.+ buried layer 15, the effect of lowering the gains of the NPN transistors 103 and 104 is also lost. Therefore, a new disadvantage arises that the gains of the NPN transistors 103 and 104 become greater than when said currents flow through the p.sup.+ buried layer 15. In addition, as the elements are made finer, the PNP transistors 101 and 102 which have been operating longitudinally become operative laterally. Thus, another disadvantage arises that the gains of the PNP transistors 101 and 102 become further increased. As a result, there has been a problem that it is impossible to effectively prevent latch-up.
More particularly, in CMOS circuits having the conventional latch-up preventive measure applied thereto, when the distance between the emitters of parasitic transistors is decreased, the carriers of the currents flowing through the NPN transistors pass through the lateral surface of the well without passing through the P.sup.+ buried layer, there has been a problem that latch-up cannot be prevented effectively by the p.sup.+ buried layer 15. Furthermore, even if an improved structure effective for preventing latch-up is newly developed, there occurs a disadvantage that the manufacturing steps of such a structure become complicated, resulting in another problem that the efficiency of production is not enhanced.